; generated by ARM C/C++ Compiler, 5.03 [Build 76]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\system_stm32f10x.o --asm_dir=.\ --list_dir=.\ --depend=.\obj\system_stm32f10x.d --cpu=Cortex-M3 --apcs=interwork -O0 -I.\FWlib\inc -I.\user -ID:\Circuits\Keil\ARM\RV31\INC -ID:\Circuits\Keil\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -ID:\Circuits\Keil\ARM\PACK\Keil\STM32F1xx_DFP\1.0.2\Device\Include -ID:\Circuits\Keil\ARM\Inc\?ST\STM32F10x -D__MICROLIB -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\obj\system_stm32f10x.crf user\system_stm32f10x.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  SetSysClockTo72 PROC
;;;676      */
;;;677    static void SetSysClockTo72(void)
000000  b50c              PUSH     {r2,r3,lr}
;;;678    {
;;;679      __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
000002  2000              MOVS     r0,#0
000004  9001              STR      r0,[sp,#4]
000006  9000              STR      r0,[sp,#0]
;;;680      
;;;681      /*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
;;;682      /*!< Enable HSE */    
;;;683      RCC->CR |= ((uint32_t)RCC_CR_HSEON);
000008  4847              LDR      r0,|L1.296|
00000a  6800              LDR      r0,[r0,#0]
00000c  f4403080          ORR      r0,r0,#0x10000
000010  4945              LDR      r1,|L1.296|
000012  6008              STR      r0,[r1,#0]
;;;684     
;;;685      /*!< Wait till HSE is ready and if Time out is reached exit */
;;;686      do
000014  bf00              NOP      
                  |L1.22|
;;;687      {
;;;688        HSEStatus = RCC->CR & RCC_CR_HSERDY;
000016  4844              LDR      r0,|L1.296|
000018  6800              LDR      r0,[r0,#0]
00001a  f4003000          AND      r0,r0,#0x20000
00001e  9000              STR      r0,[sp,#0]
;;;689        StartUpCounter++;  
000020  9801              LDR      r0,[sp,#4]
000022  1c40              ADDS     r0,r0,#1
000024  9001              STR      r0,[sp,#4]
;;;690      } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
000026  9800              LDR      r0,[sp,#0]
000028  b918              CBNZ     r0,|L1.50|
00002a  9801              LDR      r0,[sp,#4]
00002c  f5b06fa0          CMP      r0,#0x500
000030  d1f1              BNE      |L1.22|
                  |L1.50|
;;;691    
;;;692      if ((RCC->CR & RCC_CR_HSERDY) != RESET)
000032  483d              LDR      r0,|L1.296|
000034  6800              LDR      r0,[r0,#0]
000036  f4103f00          TST      r0,#0x20000
00003a  d002              BEQ      |L1.66|
;;;693      {
;;;694        HSEStatus = (uint32_t)0x01;
00003c  2001              MOVS     r0,#1
00003e  9000              STR      r0,[sp,#0]
000040  e001              B        |L1.70|
                  |L1.66|
;;;695      }
;;;696      else
;;;697      {
;;;698        HSEStatus = (uint32_t)0x00;
000042  2000              MOVS     r0,#0
000044  9000              STR      r0,[sp,#0]
                  |L1.70|
;;;699      }  
;;;700    
;;;701      if (HSEStatus == (uint32_t)0x01)
000046  9800              LDR      r0,[sp,#0]
000048  2801              CMP      r0,#1
00004a  d143              BNE      |L1.212|
;;;702      {
;;;703        /*!< Enable Prefetch Buffer */
;;;704        FLASH->ACR |= FLASH_ACR_PRFTBE;
00004c  4837              LDR      r0,|L1.300|
00004e  6800              LDR      r0,[r0,#0]
000050  f0400010          ORR      r0,r0,#0x10
000054  4935              LDR      r1,|L1.300|
000056  6008              STR      r0,[r1,#0]
;;;705    
;;;706        /*!< Flash 2 wait state */
;;;707        FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
000058  4608              MOV      r0,r1
00005a  6800              LDR      r0,[r0,#0]
00005c  f0200003          BIC      r0,r0,#3
000060  6008              STR      r0,[r1,#0]
;;;708        FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
000062  4608              MOV      r0,r1
000064  6800              LDR      r0,[r0,#0]
000066  f0400002          ORR      r0,r0,#2
00006a  6008              STR      r0,[r1,#0]
;;;709     
;;;710        /*!< HCLK = SYSCLK */
;;;711        RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00006c  482e              LDR      r0,|L1.296|
00006e  6840              LDR      r0,[r0,#4]
000070  492d              LDR      r1,|L1.296|
000072  6048              STR      r0,[r1,#4]
;;;712          
;;;713        /*!< PCLK2 = HCLK */
;;;714        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
000074  4608              MOV      r0,r1
000076  6840              LDR      r0,[r0,#4]
000078  6048              STR      r0,[r1,#4]
;;;715        
;;;716        /*!< PCLK1 = HCLK */
;;;717        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00007a  4608              MOV      r0,r1
00007c  6840              LDR      r0,[r0,#4]
00007e  f4406080          ORR      r0,r0,#0x400
000082  6048              STR      r0,[r1,#4]
;;;718        
;;;719        /*!< PLLCLK = 8MHz * 9 = 72 MHz */
;;;720        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
000084  4608              MOV      r0,r1
000086  6840              LDR      r0,[r0,#4]
000088  f420107c          BIC      r0,r0,#0x3f0000
00008c  6048              STR      r0,[r1,#4]
;;;721        RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL9);
00008e  4608              MOV      r0,r1
000090  6840              LDR      r0,[r0,#4]
000092  f44010e8          ORR      r0,r0,#0x1d0000
000096  6048              STR      r0,[r1,#4]
;;;722    
;;;723        /*!< Enable PLL */
;;;724        RCC->CR |= RCC_CR_PLLON;
000098  4608              MOV      r0,r1
00009a  6800              LDR      r0,[r0,#0]
00009c  f0407080          ORR      r0,r0,#0x1000000
0000a0  6008              STR      r0,[r1,#0]
;;;725    
;;;726        /*!< Wait till PLL is ready */
;;;727        while((RCC->CR & RCC_CR_PLLRDY) == 0)
0000a2  bf00              NOP      
                  |L1.164|
0000a4  4820              LDR      r0,|L1.296|
0000a6  6800              LDR      r0,[r0,#0]
0000a8  f0107f00          TST      r0,#0x2000000
0000ac  d0fa              BEQ      |L1.164|
;;;728        {
;;;729        }
;;;730    
;;;731        /*!< Select PLL as system clock source */
;;;732        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
0000ae  481e              LDR      r0,|L1.296|
0000b0  6840              LDR      r0,[r0,#4]
0000b2  f0200003          BIC      r0,r0,#3
0000b6  491c              LDR      r1,|L1.296|
0000b8  6048              STR      r0,[r1,#4]
;;;733        RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
0000ba  4608              MOV      r0,r1
0000bc  6840              LDR      r0,[r0,#4]
0000be  f0400002          ORR      r0,r0,#2
0000c2  6048              STR      r0,[r1,#4]
;;;734    
;;;735        /*!< Wait till PLL is used as system clock source */
;;;736        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
0000c4  bf00              NOP      
                  |L1.198|
0000c6  4818              LDR      r0,|L1.296|
0000c8  6840              LDR      r0,[r0,#4]
0000ca  f000000c          AND      r0,r0,#0xc
0000ce  2808              CMP      r0,#8
0000d0  d1f9              BNE      |L1.198|
0000d2  e001              B        |L1.216|
                  |L1.212|
;;;737        {
;;;738        }
;;;739      }
;;;740      else
;;;741      { /*!< If HSE fails to start-up, the application will have wrong clock 
;;;742             configuration. User can add here some code to deal with this error */    
;;;743    
;;;744        /*!< Go to infinite loop */
;;;745        while (1)
0000d4  bf00              NOP      
                  |L1.214|
0000d6  e7fe              B        |L1.214|
                  |L1.216|
;;;746        {
;;;747        }
;;;748      }
;;;749    }
0000d8  bd0c              POP      {r2,r3,pc}
;;;750    #endif
                          ENDP

                  SetSysClock PROC
;;;190      */
;;;191    static void SetSysClock(void)
0000da  b510              PUSH     {r4,lr}
;;;192    {
;;;193    #ifdef SYSCLK_FREQ_HSE
;;;194      SetSysClockToHSE();
;;;195    #elif defined SYSCLK_FREQ_20MHz
;;;196      SetSysClockTo20();
;;;197    #elif defined SYSCLK_FREQ_36MHz
;;;198      SetSysClockTo36();
;;;199    #elif defined SYSCLK_FREQ_48MHz
;;;200      SetSysClockTo48();
;;;201    #elif defined SYSCLK_FREQ_56MHz
;;;202      SetSysClockTo56();  
;;;203    #elif defined SYSCLK_FREQ_72MHz
;;;204      SetSysClockTo72();
0000dc  f7fffffe          BL       SetSysClockTo72
;;;205    #endif
;;;206     
;;;207     /*!< If none of the define above is enabled, the HSI is used as System clock
;;;208        source (default after reset) */ 
;;;209    }
0000e0  bd10              POP      {r4,pc}
;;;210    
                          ENDP

                  SystemInit PROC
;;;160      */
;;;161    void SystemInit (void)
0000e2  b510              PUSH     {r4,lr}
;;;162    {
;;;163      /*!< RCC system reset(for debug purpose) */
;;;164      /*!< Set HSION bit λֵ83H   ڲ8M*/			  
;;;165      RCC->CR |= (uint32_t)0x00000001;	  
0000e4  4810              LDR      r0,|L1.296|
0000e6  6800              LDR      r0,[r0,#0]
0000e8  f0400001          ORR      r0,r0,#1
0000ec  490e              LDR      r1,|L1.296|
0000ee  6008              STR      r0,[r1,#0]
;;;166      /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
;;;167      RCC->CFGR &= (uint32_t)0xF8FF0000;  
0000f0  4608              MOV      r0,r1
0000f2  6840              LDR      r0,[r0,#4]
0000f4  490e              LDR      r1,|L1.304|
0000f6  4008              ANDS     r0,r0,r1
0000f8  490b              LDR      r1,|L1.296|
0000fa  6048              STR      r0,[r1,#4]
;;;168      /*!< Reset HSEON, CSSON and PLLON bits */
;;;169      RCC->CR &= (uint32_t)0xFEF6FFFF;
0000fc  4608              MOV      r0,r1
0000fe  6800              LDR      r0,[r0,#0]
000100  490c              LDR      r1,|L1.308|
000102  4008              ANDS     r0,r0,r1
000104  4908              LDR      r1,|L1.296|
000106  6008              STR      r0,[r1,#0]
;;;170      /*!< Reset HSEBYP bit */
;;;171      RCC->CR &= (uint32_t)0xFFFBFFFF;
000108  4608              MOV      r0,r1
00010a  6800              LDR      r0,[r0,#0]
00010c  f4202080          BIC      r0,r0,#0x40000
000110  6008              STR      r0,[r1,#0]
;;;172      /*!< Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
;;;173      RCC->CFGR &= (uint32_t)0xFF80FFFF;
000112  4608              MOV      r0,r1
000114  6840              LDR      r0,[r0,#4]
000116  f42000fe          BIC      r0,r0,#0x7f0000
00011a  6048              STR      r0,[r1,#4]
;;;174      /*!< Disable all interrupts */
;;;175      RCC->CIR = 0x00000000;
00011c  2000              MOVS     r0,#0
00011e  6088              STR      r0,[r1,#8]
;;;176        
;;;177      /*!< Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
;;;178      /*!< Configure the Flash Latency cycles and enable prefetch buffer */
;;;179      SetSysClock();
000120  f7fffffe          BL       SetSysClock
;;;180    
;;;181    }
000124  bd10              POP      {r4,pc}
;;;182    
                          ENDP

000126  0000              DCW      0x0000
                  |L1.296|
                          DCD      0x40021000
                  |L1.300|
                          DCD      0x40022000
                  |L1.304|
                          DCD      0xf8ff0000
                  |L1.308|
                          DCD      0xfef6ffff

                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                  SystemFrequency
                          DCD      0x044aa200
                  SystemFrequency_SysClk
                          DCD      0x044aa200
                  SystemFrequency_AHBClk
                          DCD      0x044aa200
                  SystemFrequency_APB1Clk
                          DCD      0x02255100
                  SystemFrequency_APB2Clk
                          DCD      0x044aa200
