; generated by ARM C/C++ Compiler, 5.03 [Build 76]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\stm32f10x_rcc.o --asm_dir=.\ --list_dir=.\ --depend=.\obj\stm32f10x_rcc.d --cpu=Cortex-M3 --apcs=interwork -O0 -I.\FWlib\inc -I.\user -ID:\Circuits\Keil\ARM\RV31\INC -ID:\Circuits\Keil\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -ID:\Circuits\Keil\ARM\PACK\Keil\STM32F1xx_DFP\1.0.2\Device\Include -ID:\Circuits\Keil\ARM\Inc\?ST\STM32F10x -D__MICROLIB -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\obj\stm32f10x_rcc.crf FWlib\SRC\stm32f10x_rcc.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  RCC_DeInit PROC
;;;178      */
;;;179    void RCC_DeInit(void)
000000  48dc              LDR      r0,|L1.884|
;;;180    {
;;;181      /* Set HSION bit */
;;;182      RCC->CR |= (uint32_t)0x00000001;
000002  6800              LDR      r0,[r0,#0]
000004  f0400001          ORR      r0,r0,#1
000008  49da              LDR      r1,|L1.884|
00000a  6008              STR      r0,[r1,#0]
;;;183      /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
;;;184      RCC->CFGR &= (uint32_t)0xF8FF0000;
00000c  4608              MOV      r0,r1
00000e  6840              LDR      r0,[r0,#4]
000010  49d9              LDR      r1,|L1.888|
000012  4008              ANDS     r0,r0,r1
000014  49d7              LDR      r1,|L1.884|
000016  6048              STR      r0,[r1,#4]
;;;185      
;;;186      /* Reset HSEON, CSSON and PLLON bits */
;;;187      RCC->CR &= (uint32_t)0xFEF6FFFF;
000018  4608              MOV      r0,r1
00001a  6800              LDR      r0,[r0,#0]
00001c  49d7              LDR      r1,|L1.892|
00001e  4008              ANDS     r0,r0,r1
000020  49d4              LDR      r1,|L1.884|
000022  6008              STR      r0,[r1,#0]
;;;188      /* Reset HSEBYP bit */
;;;189      RCC->CR &= (uint32_t)0xFFFBFFFF;
000024  4608              MOV      r0,r1
000026  6800              LDR      r0,[r0,#0]
000028  f4202080          BIC      r0,r0,#0x40000
00002c  6008              STR      r0,[r1,#0]
;;;190      /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
;;;191      RCC->CFGR &= (uint32_t)0xFF80FFFF;
00002e  4608              MOV      r0,r1
000030  6840              LDR      r0,[r0,#4]
000032  f42000fe          BIC      r0,r0,#0x7f0000
000036  6048              STR      r0,[r1,#4]
;;;192      /* Disable all interrupts */
;;;193      RCC->CIR = 0x00000000;
000038  2000              MOVS     r0,#0
00003a  6088              STR      r0,[r1,#8]
;;;194    }
00003c  4770              BX       lr
;;;195    
                          ENDP

                  RCC_HSEConfig PROC
;;;207      */
;;;208    void RCC_HSEConfig(uint32_t RCC_HSE)
00003e  49cd              LDR      r1,|L1.884|
;;;209    {
;;;210      /* Check the parameters */
;;;211      assert_param(IS_RCC_HSE(RCC_HSE));
;;;212      /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
;;;213      /* Reset HSEON bit */
;;;214      RCC->CR &= CR_HSEON_Reset;
000040  6809              LDR      r1,[r1,#0]
000042  f4213180          BIC      r1,r1,#0x10000
000046  4acb              LDR      r2,|L1.884|
000048  6011              STR      r1,[r2,#0]
;;;215      /* Reset HSEBYP bit */
;;;216      RCC->CR &= CR_HSEBYP_Reset;
00004a  4611              MOV      r1,r2
00004c  6809              LDR      r1,[r1,#0]
00004e  f4212180          BIC      r1,r1,#0x40000
000052  6011              STR      r1,[r2,#0]
;;;217      /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
;;;218      switch(RCC_HSE)
000054  f5b03f80          CMP      r0,#0x10000
000058  d003              BEQ      |L1.98|
00005a  f5b02f80          CMP      r0,#0x40000
00005e  d10e              BNE      |L1.126|
000060  e006              B        |L1.112|
                  |L1.98|
;;;219      {
;;;220        case RCC_HSE_ON:
;;;221          /* Set HSEON bit */
;;;222          RCC->CR |= CR_HSEON_Set;
000062  49c4              LDR      r1,|L1.884|
000064  6809              LDR      r1,[r1,#0]
000066  f4413180          ORR      r1,r1,#0x10000
00006a  4ac2              LDR      r2,|L1.884|
00006c  6011              STR      r1,[r2,#0]
;;;223          break;
00006e  e007              B        |L1.128|
                  |L1.112|
;;;224          
;;;225        case RCC_HSE_Bypass:
;;;226          /* Set HSEBYP and HSEON bits */
;;;227          RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
000070  49c0              LDR      r1,|L1.884|
000072  6809              LDR      r1,[r1,#0]
000074  f44121a0          ORR      r1,r1,#0x50000
000078  4abe              LDR      r2,|L1.884|
00007a  6011              STR      r1,[r2,#0]
;;;228          break;
00007c  e000              B        |L1.128|
                  |L1.126|
;;;229          
;;;230        default:
;;;231          break;
00007e  bf00              NOP      
                  |L1.128|
000080  bf00              NOP                            ;223
;;;232      }
;;;233    }
000082  4770              BX       lr
;;;234    
                          ENDP

                  RCC_GetFlagStatus PROC
;;;905      */
;;;906    FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
000084  b510              PUSH     {r4,lr}
;;;907    {
000086  4601              MOV      r1,r0
;;;908      uint32_t tmp = 0;
000088  2200              MOVS     r2,#0
;;;909      uint32_t statusreg = 0;
00008a  2300              MOVS     r3,#0
;;;910      FlagStatus bitstatus = RESET;
00008c  2000              MOVS     r0,#0
;;;911      /* Check the parameters */
;;;912      assert_param(IS_RCC_FLAG(RCC_FLAG));
;;;913      /* Get the RCC register index */
;;;914      tmp = RCC_FLAG >> 5;
00008e  114a              ASRS     r2,r1,#5
;;;915      if (tmp == 1)               /* The flag to check is in CR register */
000090  2a01              CMP      r2,#1
000092  d102              BNE      |L1.154|
;;;916      {
;;;917        statusreg = RCC->CR;
000094  4cb7              LDR      r4,|L1.884|
000096  6823              LDR      r3,[r4,#0]
000098  e006              B        |L1.168|
                  |L1.154|
;;;918      }
;;;919      else if (tmp == 2)          /* The flag to check is in BDCR register */
00009a  2a02              CMP      r2,#2
00009c  d102              BNE      |L1.164|
;;;920      {
;;;921        statusreg = RCC->BDCR;
00009e  4cb5              LDR      r4,|L1.884|
0000a0  6a23              LDR      r3,[r4,#0x20]
0000a2  e001              B        |L1.168|
                  |L1.164|
;;;922      }
;;;923      else                       /* The flag to check is in CSR register */
;;;924      {
;;;925        statusreg = RCC->CSR;
0000a4  4cb3              LDR      r4,|L1.884|
0000a6  6a63              LDR      r3,[r4,#0x24]
                  |L1.168|
;;;926      }
;;;927      /* Get the flag position */
;;;928      tmp = RCC_FLAG & FLAG_Mask;
0000a8  f001021f          AND      r2,r1,#0x1f
;;;929      if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
0000ac  2401              MOVS     r4,#1
0000ae  4094              LSLS     r4,r4,r2
0000b0  421c              TST      r4,r3
0000b2  d001              BEQ      |L1.184|
;;;930      {
;;;931        bitstatus = SET;
0000b4  2001              MOVS     r0,#1
0000b6  e000              B        |L1.186|
                  |L1.184|
;;;932      }
;;;933      else
;;;934      {
;;;935        bitstatus = RESET;
0000b8  2000              MOVS     r0,#0
                  |L1.186|
;;;936      }
;;;937      /* Return the flag status */
;;;938      return bitstatus;
;;;939    }
0000ba  bd10              POP      {r4,pc}
;;;940    
                          ENDP

                  RCC_WaitForHSEStartUp PROC
;;;241      */
;;;242    ErrorStatus RCC_WaitForHSEStartUp(void)
0000bc  b538              PUSH     {r3-r5,lr}
;;;243    {
;;;244      __IO uint32_t StartUpCounter = 0;
0000be  2000              MOVS     r0,#0
0000c0  9000              STR      r0,[sp,#0]
;;;245      ErrorStatus status = ERROR;
0000c2  2400              MOVS     r4,#0
;;;246      FlagStatus HSEStatus = RESET;
0000c4  2500              MOVS     r5,#0
;;;247      
;;;248      /* Wait till HSE is ready and if Time out is reached exit */
;;;249      do
0000c6  bf00              NOP      
                  |L1.200|
;;;250      {
;;;251        HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
0000c8  2031              MOVS     r0,#0x31
0000ca  f7fffffe          BL       RCC_GetFlagStatus
0000ce  4605              MOV      r5,r0
;;;252        StartUpCounter++;  
0000d0  9800              LDR      r0,[sp,#0]
0000d2  1c40              ADDS     r0,r0,#1
0000d4  9000              STR      r0,[sp,#0]
;;;253      } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));
0000d6  b91d              CBNZ     r5,|L1.224|
0000d8  9800              LDR      r0,[sp,#0]
0000da  f5b06fa0          CMP      r0,#0x500
0000de  d1f3              BNE      |L1.200|
                  |L1.224|
;;;254      if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
0000e0  2031              MOVS     r0,#0x31
0000e2  f7fffffe          BL       RCC_GetFlagStatus
0000e6  b108              CBZ      r0,|L1.236|
;;;255      {
;;;256        status = SUCCESS;
0000e8  2401              MOVS     r4,#1
0000ea  e000              B        |L1.238|
                  |L1.236|
;;;257      }
;;;258      else
;;;259      {
;;;260        status = ERROR;
0000ec  2400              MOVS     r4,#0
                  |L1.238|
;;;261      }  
;;;262      return (status);
0000ee  4620              MOV      r0,r4
;;;263    }
0000f0  bd38              POP      {r3-r5,pc}
;;;264    
                          ENDP

                  RCC_AdjustHSICalibrationValue PROC
;;;271      */
;;;272    void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
0000f2  4601              MOV      r1,r0
;;;273    {
;;;274      uint32_t tmpreg = 0;
0000f4  2000              MOVS     r0,#0
;;;275      /* Check the parameters */
;;;276      assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
;;;277      tmpreg = RCC->CR;
0000f6  4a9f              LDR      r2,|L1.884|
0000f8  6810              LDR      r0,[r2,#0]
;;;278      /* Clear HSITRIM[4:0] bits */
;;;279      tmpreg &= CR_HSITRIM_Mask;
0000fa  f02000f8          BIC      r0,r0,#0xf8
;;;280      /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
;;;281      tmpreg |= (uint32_t)HSICalibrationValue << 3;
0000fe  ea4000c1          ORR      r0,r0,r1,LSL #3
;;;282      /* Store the new value */
;;;283      RCC->CR = tmpreg;
000102  6010              STR      r0,[r2,#0]
;;;284    }
000104  4770              BX       lr
;;;285    
                          ENDP

                  RCC_HSICmd PROC
;;;293      */
;;;294    void RCC_HSICmd(FunctionalState NewState)
000106  499e              LDR      r1,|L1.896|
;;;295    {
;;;296      /* Check the parameters */
;;;297      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;298      *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
000108  6008              STR      r0,[r1,#0]
;;;299    }
00010a  4770              BX       lr
;;;300    
                          ENDP

                  RCC_PLLConfig PROC
;;;315      */
;;;316    void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
00010c  4602              MOV      r2,r0
;;;317    {
;;;318      uint32_t tmpreg = 0;
00010e  2000              MOVS     r0,#0
;;;319      /* Check the parameters */
;;;320      assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
;;;321      assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
;;;322      tmpreg = RCC->CFGR;
000110  4b98              LDR      r3,|L1.884|
000112  6858              LDR      r0,[r3,#4]
;;;323      /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
;;;324      tmpreg &= CFGR_PLL_Mask;
000114  f420107c          BIC      r0,r0,#0x3f0000
;;;325      /* Set the PLL configuration bits */
;;;326      tmpreg |= RCC_PLLSource | RCC_PLLMul;
000118  ea420301          ORR      r3,r2,r1
00011c  4318              ORRS     r0,r0,r3
;;;327      /* Store the new value */
;;;328      RCC->CFGR = tmpreg;
00011e  4b95              LDR      r3,|L1.884|
000120  6058              STR      r0,[r3,#4]
;;;329    }
000122  4770              BX       lr
;;;330    
                          ENDP

                  RCC_PLLCmd PROC
;;;337      */
;;;338    void RCC_PLLCmd(FunctionalState NewState)
000124  4996              LDR      r1,|L1.896|
;;;339    {
;;;340      /* Check the parameters */
;;;341      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;342      *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
000126  6608              STR      r0,[r1,#0x60]
;;;343    }
000128  4770              BX       lr
;;;344    
                          ENDP

                  RCC_SYSCLKConfig PROC
;;;353      */
;;;354    void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
00012a  4601              MOV      r1,r0
;;;355    {
;;;356      uint32_t tmpreg = 0;
00012c  2000              MOVS     r0,#0
;;;357      /* Check the parameters */
;;;358      assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
;;;359      tmpreg = RCC->CFGR;
00012e  4a91              LDR      r2,|L1.884|
000130  6850              LDR      r0,[r2,#4]
;;;360      /* Clear SW[1:0] bits */
;;;361      tmpreg &= CFGR_SW_Mask;
000132  f0200003          BIC      r0,r0,#3
;;;362      /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
;;;363      tmpreg |= RCC_SYSCLKSource;
000136  4308              ORRS     r0,r0,r1
;;;364      /* Store the new value */
;;;365      RCC->CFGR = tmpreg;
000138  6050              STR      r0,[r2,#4]
;;;366    }
00013a  4770              BX       lr
;;;367    
                          ENDP

                  RCC_GetSYSCLKSource PROC
;;;376      */
;;;377    uint8_t RCC_GetSYSCLKSource(void)
00013c  488d              LDR      r0,|L1.884|
;;;378    {
;;;379      return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
00013e  6840              LDR      r0,[r0,#4]
000140  f000000c          AND      r0,r0,#0xc
;;;380    }
000144  4770              BX       lr
;;;381    
                          ENDP

                  RCC_HCLKConfig PROC
;;;397      */
;;;398    void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
000146  4601              MOV      r1,r0
;;;399    {
;;;400      uint32_t tmpreg = 0;
000148  2000              MOVS     r0,#0
;;;401      /* Check the parameters */
;;;402      assert_param(IS_RCC_HCLK(RCC_SYSCLK));
;;;403      tmpreg = RCC->CFGR;
00014a  4a8a              LDR      r2,|L1.884|
00014c  6850              LDR      r0,[r2,#4]
;;;404      /* Clear HPRE[3:0] bits */
;;;405      tmpreg &= CFGR_HPRE_Reset_Mask;
00014e  f02000f0          BIC      r0,r0,#0xf0
;;;406      /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
;;;407      tmpreg |= RCC_SYSCLK;
000152  4308              ORRS     r0,r0,r1
;;;408      /* Store the new value */
;;;409      RCC->CFGR = tmpreg;
000154  6050              STR      r0,[r2,#4]
;;;410    }
000156  4770              BX       lr
;;;411    
                          ENDP

                  RCC_PCLK1Config PROC
;;;423      */
;;;424    void RCC_PCLK1Config(uint32_t RCC_HCLK)
000158  4601              MOV      r1,r0
;;;425    {
;;;426      uint32_t tmpreg = 0;
00015a  2000              MOVS     r0,#0
;;;427      /* Check the parameters */
;;;428      assert_param(IS_RCC_PCLK(RCC_HCLK));
;;;429      tmpreg = RCC->CFGR;
00015c  4a85              LDR      r2,|L1.884|
00015e  6850              LDR      r0,[r2,#4]
;;;430      /* Clear PPRE1[2:0] bits */
;;;431      tmpreg &= CFGR_PPRE1_Reset_Mask;
000160  f42060e0          BIC      r0,r0,#0x700
;;;432      /* Set PPRE1[2:0] bits according to RCC_HCLK value */
;;;433      tmpreg |= RCC_HCLK;
000164  4308              ORRS     r0,r0,r1
;;;434      /* Store the new value */
;;;435      RCC->CFGR = tmpreg;
000166  6050              STR      r0,[r2,#4]
;;;436    }
000168  4770              BX       lr
;;;437    
                          ENDP

                  RCC_PCLK2Config PROC
;;;449      */
;;;450    void RCC_PCLK2Config(uint32_t RCC_HCLK)
00016a  4601              MOV      r1,r0
;;;451    {
;;;452      uint32_t tmpreg = 0;
00016c  2000              MOVS     r0,#0
;;;453      /* Check the parameters */
;;;454      assert_param(IS_RCC_PCLK(RCC_HCLK));
;;;455      tmpreg = RCC->CFGR;
00016e  4a81              LDR      r2,|L1.884|
000170  6850              LDR      r0,[r2,#4]
;;;456      /* Clear PPRE2[2:0] bits */
;;;457      tmpreg &= CFGR_PPRE2_Reset_Mask;
000172  f4205060          BIC      r0,r0,#0x3800
;;;458      /* Set PPRE2[2:0] bits according to RCC_HCLK value */
;;;459      tmpreg |= RCC_HCLK << 3;
000176  ea4000c1          ORR      r0,r0,r1,LSL #3
;;;460      /* Store the new value */
;;;461      RCC->CFGR = tmpreg;
00017a  6050              STR      r0,[r2,#4]
;;;462    }
00017c  4770              BX       lr
;;;463    
                          ENDP

                  RCC_ITConfig PROC
;;;476      */
;;;477    void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
00017e  b129              CBZ      r1,|L1.396|
;;;478    {
;;;479      /* Check the parameters */
;;;480      assert_param(IS_RCC_IT(RCC_IT));
;;;481      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;482      if (NewState != DISABLE)
;;;483      {
;;;484        /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
;;;485        *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
000180  4a7c              LDR      r2,|L1.884|
000182  7a52              LDRB     r2,[r2,#9]
000184  4302              ORRS     r2,r2,r0
000186  4b7b              LDR      r3,|L1.884|
000188  725a              STRB     r2,[r3,#9]
00018a  e004              B        |L1.406|
                  |L1.396|
;;;486      }
;;;487      else
;;;488      {
;;;489        /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
;;;490        *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
00018c  4a79              LDR      r2,|L1.884|
00018e  7a52              LDRB     r2,[r2,#9]
000190  4382              BICS     r2,r2,r0
000192  4b78              LDR      r3,|L1.884|
000194  725a              STRB     r2,[r3,#9]
                  |L1.406|
;;;491      }
;;;492    }
000196  4770              BX       lr
;;;493    
                          ENDP

                  RCC_USBCLKConfig PROC
;;;503      */
;;;504    void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
000198  497a              LDR      r1,|L1.900|
;;;505    {
;;;506      /* Check the parameters */
;;;507      assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
;;;508      *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
00019a  6008              STR      r0,[r1,#0]
;;;509    }
00019c  4770              BX       lr
;;;510    
                          ENDP

                  RCC_ADCCLKConfig PROC
;;;521      */
;;;522    void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
00019e  4601              MOV      r1,r0
;;;523    {
;;;524      uint32_t tmpreg = 0;
0001a0  2000              MOVS     r0,#0
;;;525      /* Check the parameters */
;;;526      assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
;;;527      tmpreg = RCC->CFGR;
0001a2  4a74              LDR      r2,|L1.884|
0001a4  6850              LDR      r0,[r2,#4]
;;;528      /* Clear ADCPRE[1:0] bits */
;;;529      tmpreg &= CFGR_ADCPRE_Reset_Mask;
0001a6  f4204040          BIC      r0,r0,#0xc000
;;;530      /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
;;;531      tmpreg |= RCC_PCLK2;
0001aa  4308              ORRS     r0,r0,r1
;;;532      /* Store the new value */
;;;533      RCC->CFGR = tmpreg;
0001ac  6050              STR      r0,[r2,#4]
;;;534    }
0001ae  4770              BX       lr
;;;535    
                          ENDP

                  RCC_LSEConfig PROC
;;;545      */
;;;546    void RCC_LSEConfig(uint8_t RCC_LSE)
0001b0  2100              MOVS     r1,#0
;;;547    {
;;;548      /* Check the parameters */
;;;549      assert_param(IS_RCC_LSE(RCC_LSE));
;;;550      /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
;;;551      /* Reset LSEON bit */
;;;552      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
0001b2  4a75              LDR      r2,|L1.904|
0001b4  7011              STRB     r1,[r2,#0]
;;;553      /* Reset LSEBYP bit */
;;;554      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
0001b6  4a6f              LDR      r2,|L1.884|
0001b8  f8821020          STRB     r1,[r2,#0x20]
;;;555      /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
;;;556      switch(RCC_LSE)
0001bc  2801              CMP      r0,#1
0001be  d002              BEQ      |L1.454|
0001c0  2804              CMP      r0,#4
0001c2  d108              BNE      |L1.470|
0001c4  e003              B        |L1.462|
                  |L1.454|
;;;557      {
;;;558        case RCC_LSE_ON:
;;;559          /* Set LSEON bit */
;;;560          *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
0001c6  2101              MOVS     r1,#1
0001c8  4a6f              LDR      r2,|L1.904|
0001ca  7011              STRB     r1,[r2,#0]
;;;561          break;
0001cc  e004              B        |L1.472|
                  |L1.462|
;;;562          
;;;563        case RCC_LSE_Bypass:
;;;564          /* Set LSEBYP and LSEON bits */
;;;565          *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
0001ce  2105              MOVS     r1,#5
0001d0  4a6d              LDR      r2,|L1.904|
0001d2  7011              STRB     r1,[r2,#0]
;;;566          break;            
0001d4  e000              B        |L1.472|
                  |L1.470|
;;;567          
;;;568        default:
;;;569          break;      
0001d6  bf00              NOP      
                  |L1.472|
0001d8  bf00              NOP                            ;561
;;;570      }
;;;571    }
0001da  4770              BX       lr
;;;572    
                          ENDP

                  RCC_LSICmd PROC
;;;579      */
;;;580    void RCC_LSICmd(FunctionalState NewState)
0001dc  496b              LDR      r1,|L1.908|
;;;581    {
;;;582      /* Check the parameters */
;;;583      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;584      *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
0001de  6008              STR      r0,[r1,#0]
;;;585    }
0001e0  4770              BX       lr
;;;586    
                          ENDP

                  RCC_RTCCLKConfig PROC
;;;598      */
;;;599    void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
0001e2  4964              LDR      r1,|L1.884|
;;;600    {
;;;601      /* Check the parameters */
;;;602      assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
;;;603      /* Select the RTC clock source */
;;;604      RCC->BDCR |= RCC_RTCCLKSource;
0001e4  6a09              LDR      r1,[r1,#0x20]
0001e6  4301              ORRS     r1,r1,r0
0001e8  4a62              LDR      r2,|L1.884|
0001ea  6211              STR      r1,[r2,#0x20]
;;;605    }
0001ec  4770              BX       lr
;;;606    
                          ENDP

                  RCC_RTCCLKCmd PROC
;;;614      */
;;;615    void RCC_RTCCLKCmd(FunctionalState NewState)
0001ee  4967              LDR      r1,|L1.908|
;;;616    {
;;;617      /* Check the parameters */
;;;618      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;619      *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
0001f0  3944              SUBS     r1,r1,#0x44
0001f2  6008              STR      r0,[r1,#0]
;;;620    }
0001f4  4770              BX       lr
;;;621    
                          ENDP

                  RCC_GetClocksFreq PROC
;;;627      */
;;;628    void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
0001f6  b530              PUSH     {r4,r5,lr}
;;;629    {
;;;630      uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
0001f8  2100              MOVS     r1,#0
0001fa  2200              MOVS     r2,#0
0001fc  2400              MOVS     r4,#0
0001fe  2300              MOVS     r3,#0
;;;631      /* Get SYSCLK source -------------------------------------------------------*/
;;;632      tmp = RCC->CFGR & CFGR_SWS_Mask;
000200  4d5c              LDR      r5,|L1.884|
000202  686d              LDR      r5,[r5,#4]
000204  f005010c          AND      r1,r5,#0xc
;;;633      switch (tmp)
000208  b121              CBZ      r1,|L1.532|
00020a  2904              CMP      r1,#4
00020c  d005              BEQ      |L1.538|
00020e  2908              CMP      r1,#8
000210  d123              BNE      |L1.602|
000212  e005              B        |L1.544|
                  |L1.532|
;;;634      {
;;;635        case 0x00:  /* HSI used as system clock */
;;;636          RCC_Clocks->SYSCLK_Frequency = HSI_Value;
000214  4d5e              LDR      r5,|L1.912|
000216  6005              STR      r5,[r0,#0]
;;;637          break;
000218  e022              B        |L1.608|
                  |L1.538|
;;;638        case 0x04:  /* HSE used as system clock */
;;;639          RCC_Clocks->SYSCLK_Frequency = HSE_Value;
00021a  4d5d              LDR      r5,|L1.912|
00021c  6005              STR      r5,[r0,#0]
;;;640          break;
00021e  e01f              B        |L1.608|
                  |L1.544|
;;;641        case 0x08:  /* PLL used as system clock */
;;;642          /* Get PLL clock source and multiplication factor ----------------------*/
;;;643          pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
000220  4d54              LDR      r5,|L1.884|
000222  686d              LDR      r5,[r5,#4]
000224  f4051270          AND      r2,r5,#0x3c0000
;;;644          pllmull = ( pllmull >> 18) + 2;
000228  2502              MOVS     r5,#2
00022a  eb054292          ADD      r2,r5,r2,LSR #18
;;;645          pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
00022e  4d51              LDR      r5,|L1.884|
000230  686d              LDR      r5,[r5,#4]
000232  f4053480          AND      r4,r5,#0x10000
;;;646          if (pllsource == 0x00)
000236  b91c              CBNZ     r4,|L1.576|
;;;647          {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;648            RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
000238  4d56              LDR      r5,|L1.916|
00023a  4355              MULS     r5,r2,r5
00023c  6005              STR      r5,[r0,#0]
00023e  e00b              B        |L1.600|
                  |L1.576|
;;;649          }
;;;650          else
;;;651          {/* HSE selected as PLL clock entry */
;;;652            if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
000240  4d4c              LDR      r5,|L1.884|
000242  686d              LDR      r5,[r5,#4]
000244  f4153f00          TST      r5,#0x20000
000248  d003              BEQ      |L1.594|
;;;653            {/* HSE oscillator clock divided by 2 */
;;;654              RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
00024a  4d52              LDR      r5,|L1.916|
00024c  4355              MULS     r5,r2,r5
00024e  6005              STR      r5,[r0,#0]
000250  e002              B        |L1.600|
                  |L1.594|
;;;655            }
;;;656            else
;;;657            {
;;;658              RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
000252  4d4f              LDR      r5,|L1.912|
000254  4355              MULS     r5,r2,r5
000256  6005              STR      r5,[r0,#0]
                  |L1.600|
;;;659            }
;;;660          }
;;;661          break;
000258  e002              B        |L1.608|
                  |L1.602|
;;;662        default:
;;;663          RCC_Clocks->SYSCLK_Frequency = HSI_Value;
00025a  4d4d              LDR      r5,|L1.912|
00025c  6005              STR      r5,[r0,#0]
;;;664          break;
00025e  bf00              NOP      
                  |L1.608|
000260  bf00              NOP                            ;637
;;;665      }
;;;666      /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
;;;667      /* Get HCLK prescaler */
;;;668      tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
000262  4d44              LDR      r5,|L1.884|
000264  686d              LDR      r5,[r5,#4]
000266  f00501f0          AND      r1,r5,#0xf0
;;;669      tmp = tmp >> 4;
00026a  0909              LSRS     r1,r1,#4
;;;670      presc = APBAHBPrescTable[tmp];
00026c  4d4a              LDR      r5,|L1.920|
00026e  5c6b              LDRB     r3,[r5,r1]
;;;671      /* HCLK clock frequency */
;;;672      RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
000270  6805              LDR      r5,[r0,#0]
000272  40dd              LSRS     r5,r5,r3
000274  6045              STR      r5,[r0,#4]
;;;673      /* Get PCLK1 prescaler */
;;;674      tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
000276  4d3f              LDR      r5,|L1.884|
000278  686d              LDR      r5,[r5,#4]
00027a  f40561e0          AND      r1,r5,#0x700
;;;675      tmp = tmp >> 8;
00027e  0a09              LSRS     r1,r1,#8
;;;676      presc = APBAHBPrescTable[tmp];
000280  4d45              LDR      r5,|L1.920|
000282  5c6b              LDRB     r3,[r5,r1]
;;;677      /* PCLK1 clock frequency */
;;;678      RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
000284  6845              LDR      r5,[r0,#4]
000286  40dd              LSRS     r5,r5,r3
000288  6085              STR      r5,[r0,#8]
;;;679      /* Get PCLK2 prescaler */
;;;680      tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
00028a  4d3a              LDR      r5,|L1.884|
00028c  686d              LDR      r5,[r5,#4]
00028e  f4055160          AND      r1,r5,#0x3800
;;;681      tmp = tmp >> 11;
000292  0ac9              LSRS     r1,r1,#11
;;;682      presc = APBAHBPrescTable[tmp];
000294  4d40              LDR      r5,|L1.920|
000296  5c6b              LDRB     r3,[r5,r1]
;;;683      /* PCLK2 clock frequency */
;;;684      RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
000298  6845              LDR      r5,[r0,#4]
00029a  40dd              LSRS     r5,r5,r3
00029c  60c5              STR      r5,[r0,#0xc]
;;;685      /* Get ADCCLK prescaler */
;;;686      tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
00029e  4d35              LDR      r5,|L1.884|
0002a0  686d              LDR      r5,[r5,#4]
0002a2  f4054140          AND      r1,r5,#0xc000
;;;687      tmp = tmp >> 14;
0002a6  0b89              LSRS     r1,r1,#14
;;;688      presc = ADCPrescTable[tmp];
0002a8  4d3c              LDR      r5,|L1.924|
0002aa  5c6b              LDRB     r3,[r5,r1]
;;;689      /* ADCCLK clock frequency */
;;;690      RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
0002ac  68c5              LDR      r5,[r0,#0xc]
0002ae  fbb5f5f3          UDIV     r5,r5,r3
0002b2  6105              STR      r5,[r0,#0x10]
;;;691    }
0002b4  bd30              POP      {r4,r5,pc}
;;;692    
                          ENDP

                  RCC_AHBPeriphClockCmd PROC
;;;708      */
;;;709    void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
0002b6  b129              CBZ      r1,|L1.708|
;;;710    {
;;;711      /* Check the parameters */
;;;712      assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
;;;713      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;714      if (NewState != DISABLE)
;;;715      {
;;;716        RCC->AHBENR |= RCC_AHBPeriph;
0002b8  4a2e              LDR      r2,|L1.884|
0002ba  6952              LDR      r2,[r2,#0x14]
0002bc  4302              ORRS     r2,r2,r0
0002be  4b2d              LDR      r3,|L1.884|
0002c0  615a              STR      r2,[r3,#0x14]
0002c2  e004              B        |L1.718|
                  |L1.708|
;;;717      }
;;;718      else
;;;719      {
;;;720        RCC->AHBENR &= ~RCC_AHBPeriph;
0002c4  4a2b              LDR      r2,|L1.884|
0002c6  6952              LDR      r2,[r2,#0x14]
0002c8  4382              BICS     r2,r2,r0
0002ca  4b2a              LDR      r3,|L1.884|
0002cc  615a              STR      r2,[r3,#0x14]
                  |L1.718|
;;;721      }
;;;722    }
0002ce  4770              BX       lr
;;;723    
                          ENDP

                  RCC_APB2PeriphClockCmd PROC
;;;738      */
;;;739    void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
0002d0  b129              CBZ      r1,|L1.734|
;;;740    {
;;;741      /* Check the parameters */
;;;742      assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;743      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;744      if (NewState != DISABLE)
;;;745      {
;;;746        RCC->APB2ENR |= RCC_APB2Periph;
0002d2  4a28              LDR      r2,|L1.884|
0002d4  6992              LDR      r2,[r2,#0x18]
0002d6  4302              ORRS     r2,r2,r0
0002d8  4b26              LDR      r3,|L1.884|
0002da  619a              STR      r2,[r3,#0x18]
0002dc  e004              B        |L1.744|
                  |L1.734|
;;;747      }
;;;748      else
;;;749      {
;;;750        RCC->APB2ENR &= ~RCC_APB2Periph;
0002de  4a25              LDR      r2,|L1.884|
0002e0  6992              LDR      r2,[r2,#0x18]
0002e2  4382              BICS     r2,r2,r0
0002e4  4b23              LDR      r3,|L1.884|
0002e6  619a              STR      r2,[r3,#0x18]
                  |L1.744|
;;;751      }
;;;752    }
0002e8  4770              BX       lr
;;;753    
                          ENDP

                  RCC_APB1PeriphClockCmd PROC
;;;769      */
;;;770    void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
0002ea  b129              CBZ      r1,|L1.760|
;;;771    {
;;;772      /* Check the parameters */
;;;773      assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;774      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;775      if (NewState != DISABLE)
;;;776      {
;;;777        RCC->APB1ENR |= RCC_APB1Periph;
0002ec  4a21              LDR      r2,|L1.884|
0002ee  69d2              LDR      r2,[r2,#0x1c]
0002f0  4302              ORRS     r2,r2,r0
0002f2  4b20              LDR      r3,|L1.884|
0002f4  61da              STR      r2,[r3,#0x1c]
0002f6  e004              B        |L1.770|
                  |L1.760|
;;;778      }
;;;779      else
;;;780      {
;;;781        RCC->APB1ENR &= ~RCC_APB1Periph;
0002f8  4a1e              LDR      r2,|L1.884|
0002fa  69d2              LDR      r2,[r2,#0x1c]
0002fc  4382              BICS     r2,r2,r0
0002fe  4b1d              LDR      r3,|L1.884|
000300  61da              STR      r2,[r3,#0x1c]
                  |L1.770|
;;;782      }
;;;783    }
000302  4770              BX       lr
;;;784    
                          ENDP

                  RCC_APB2PeriphResetCmd PROC
;;;798      */
;;;799    void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
000304  b129              CBZ      r1,|L1.786|
;;;800    {
;;;801      /* Check the parameters */
;;;802      assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;803      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;804      if (NewState != DISABLE)
;;;805      {
;;;806        RCC->APB2RSTR |= RCC_APB2Periph;
000306  4a1b              LDR      r2,|L1.884|
000308  68d2              LDR      r2,[r2,#0xc]
00030a  4302              ORRS     r2,r2,r0
00030c  4b19              LDR      r3,|L1.884|
00030e  60da              STR      r2,[r3,#0xc]
000310  e004              B        |L1.796|
                  |L1.786|
;;;807      }
;;;808      else
;;;809      {
;;;810        RCC->APB2RSTR &= ~RCC_APB2Periph;
000312  4a18              LDR      r2,|L1.884|
000314  68d2              LDR      r2,[r2,#0xc]
000316  4382              BICS     r2,r2,r0
000318  4b16              LDR      r3,|L1.884|
00031a  60da              STR      r2,[r3,#0xc]
                  |L1.796|
;;;811      }
;;;812    }
00031c  4770              BX       lr
;;;813    
                          ENDP

                  RCC_APB1PeriphResetCmd PROC
;;;828      */
;;;829    void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
00031e  b129              CBZ      r1,|L1.812|
;;;830    {
;;;831      /* Check the parameters */
;;;832      assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;833      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;834      if (NewState != DISABLE)
;;;835      {
;;;836        RCC->APB1RSTR |= RCC_APB1Periph;
000320  4a14              LDR      r2,|L1.884|
000322  6912              LDR      r2,[r2,#0x10]
000324  4302              ORRS     r2,r2,r0
000326  4b13              LDR      r3,|L1.884|
000328  611a              STR      r2,[r3,#0x10]
00032a  e004              B        |L1.822|
                  |L1.812|
;;;837      }
;;;838      else
;;;839      {
;;;840        RCC->APB1RSTR &= ~RCC_APB1Periph;
00032c  4a11              LDR      r2,|L1.884|
00032e  6912              LDR      r2,[r2,#0x10]
000330  4382              BICS     r2,r2,r0
000332  4b10              LDR      r3,|L1.884|
000334  611a              STR      r2,[r3,#0x10]
                  |L1.822|
;;;841      }
;;;842    }
000336  4770              BX       lr
;;;843    
                          ENDP

                  RCC_BackupResetCmd PROC
;;;849      */
;;;850    void RCC_BackupResetCmd(FunctionalState NewState)
000338  4914              LDR      r1,|L1.908|
;;;851    {
;;;852      /* Check the parameters */
;;;853      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;854      *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
00033a  3940              SUBS     r1,r1,#0x40
00033c  6008              STR      r0,[r1,#0]
;;;855    }
00033e  4770              BX       lr
;;;856    
                          ENDP

                  RCC_ClockSecuritySystemCmd PROC
;;;862      */
;;;863    void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
000340  490f              LDR      r1,|L1.896|
;;;864    {
;;;865      /* Check the parameters */
;;;866      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;867      *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
000342  64c8              STR      r0,[r1,#0x4c]
;;;868    }
000344  4770              BX       lr
;;;869    
                          ENDP

                  RCC_MCOConfig PROC
;;;880      */
;;;881    void RCC_MCOConfig(uint8_t RCC_MCO)
000346  490b              LDR      r1,|L1.884|
;;;882    {
;;;883      /* Check the parameters */
;;;884      assert_param(IS_RCC_MCO(RCC_MCO));
;;;885      /* Perform Byte access to MCO[2:0] bits to select the MCO source */
;;;886      *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
000348  71c8              STRB     r0,[r1,#7]
;;;887    }
00034a  4770              BX       lr
;;;888    
                          ENDP

                  RCC_ClearFlag PROC
;;;948      */
;;;949    void RCC_ClearFlag(void)
00034c  4809              LDR      r0,|L1.884|
;;;950    {
;;;951      /* Set RMVF bit to clear the reset flags */
;;;952      RCC->CSR |= CSR_RMVF_Set;
00034e  6a40              LDR      r0,[r0,#0x24]
000350  f0407080          ORR      r0,r0,#0x1000000
000354  4907              LDR      r1,|L1.884|
000356  6248              STR      r0,[r1,#0x24]
;;;953    }
000358  4770              BX       lr
;;;954    
                          ENDP

                  RCC_GetITStatus PROC
;;;966      */
;;;967    ITStatus RCC_GetITStatus(uint8_t RCC_IT)
00035a  4601              MOV      r1,r0
;;;968    {
;;;969      ITStatus bitstatus = RESET;
00035c  2000              MOVS     r0,#0
;;;970      /* Check the parameters */
;;;971      assert_param(IS_RCC_GET_IT(RCC_IT));
;;;972      /* Check the status of the specified RCC interrupt */
;;;973      if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
00035e  4a05              LDR      r2,|L1.884|
000360  6892              LDR      r2,[r2,#8]
000362  420a              TST      r2,r1
000364  d001              BEQ      |L1.874|
;;;974      {
;;;975        bitstatus = SET;
000366  2001              MOVS     r0,#1
000368  e000              B        |L1.876|
                  |L1.874|
;;;976      }
;;;977      else
;;;978      {
;;;979        bitstatus = RESET;
00036a  2000              MOVS     r0,#0
                  |L1.876|
;;;980      }
;;;981      /* Return the RCC_IT status */
;;;982      return  bitstatus;
;;;983    }
00036c  4770              BX       lr
;;;984    
                          ENDP

                  RCC_ClearITPendingBit PROC
;;;996      */
;;;997    void RCC_ClearITPendingBit(uint8_t RCC_IT)
00036e  4901              LDR      r1,|L1.884|
;;;998    {
;;;999      /* Check the parameters */
;;;1000     assert_param(IS_RCC_CLEAR_IT(RCC_IT));
;;;1001     /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
;;;1002        pending bits */
;;;1003     *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
000370  7288              STRB     r0,[r1,#0xa]
;;;1004   }
000372  4770              BX       lr
;;;1005   
                          ENDP

                  |L1.884|
                          DCD      0x40021000
                  |L1.888|
                          DCD      0xf8ff0000
                  |L1.892|
                          DCD      0xfef6ffff
                  |L1.896|
                          DCD      0x42420000
                  |L1.900|
                          DCD      0x424200d8
                  |L1.904|
                          DCD      0x40021020
                  |L1.908|
                          DCD      0x42420480
                  |L1.912|
                          DCD      0x007a1200
                  |L1.916|
                          DCD      0x003d0900
                  |L1.920|
                          DCD      APBAHBPrescTable
                  |L1.924|
                          DCD      ADCPrescTable

                          AREA ||.data||, DATA, ALIGN=0

                  APBAHBPrescTable
000000  00000000          DCB      0x00,0x00,0x00,0x00
000004  01020304          DCB      0x01,0x02,0x03,0x04
000008  01020304          DCB      0x01,0x02,0x03,0x04
00000c  06070809          DCB      0x06,0x07,0x08,0x09
                  ADCPrescTable
000010  02040608          DCB      0x02,0x04,0x06,0x08
