; generated by ARM C/C++ Compiler, 4.1 [Build 481]
; commandline ArmCC [--debug -c --asm --interleave -o.\Obj\system_stm32f10x.o --depend=.\Obj\system_stm32f10x.d --cpu=Cortex-M3 --apcs=interwork -O0 -I.\FWlib\inc -I.\user -Id:\Keil\ARM\INC -Id:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DUSE_STDPERIPH_DRIVER -DSTM32F10X_HD --omf_browse=.\Obj\system_stm32f10x.crf user\system_stm32f10x.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  SetSysClockTo72 PROC
;;;676      */
;;;677    static void SetSysClockTo72(void)
000000  2100              MOVS     r1,#0
;;;678    {
;;;679      __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
000002  2000              MOVS     r0,#0
;;;680      
;;;681      /*!< SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
;;;682      /*!< Enable HSE */    
;;;683      RCC->CR |= ((uint32_t)RCC_CR_HSEON);
000004  4a43              LDR      r2,|L1.276|
000006  6812              LDR      r2,[r2,#0]
000008  f4423280          ORR      r2,r2,#0x10000
00000c  4b41              LDR      r3,|L1.276|
00000e  601a              STR      r2,[r3,#0]
;;;684     
;;;685      /*!< Wait till HSE is ready and if Time out is reached exit */
;;;686      do
000010  bf00              NOP      
                  |L1.18|
;;;687      {
;;;688        HSEStatus = RCC->CR & RCC_CR_HSERDY;
000012  4a40              LDR      r2,|L1.276|
000014  6812              LDR      r2,[r2,#0]
000016  f4023000          AND      r0,r2,#0x20000
;;;689        StartUpCounter++;  
00001a  1c49              ADDS     r1,r1,#1
;;;690      } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
00001c  b910              CBNZ     r0,|L1.36|
00001e  f5b16fa0          CMP      r1,#0x500
000022  d1f6              BNE      |L1.18|
                  |L1.36|
;;;691    
;;;692      if ((RCC->CR & RCC_CR_HSERDY) != RESET)
000024  4a3b              LDR      r2,|L1.276|
000026  6812              LDR      r2,[r2,#0]
000028  f4123f00          TST      r2,#0x20000
00002c  d001              BEQ      |L1.50|
;;;693      {
;;;694        HSEStatus = (uint32_t)0x01;
00002e  2001              MOVS     r0,#1
000030  e000              B        |L1.52|
                  |L1.50|
;;;695      }
;;;696      else
;;;697      {
;;;698        HSEStatus = (uint32_t)0x00;
000032  2000              MOVS     r0,#0
                  |L1.52|
;;;699      }  
;;;700    
;;;701      if (HSEStatus == (uint32_t)0x01)
000034  2801              CMP      r0,#1
000036  d143              BNE      |L1.192|
;;;702      {
;;;703        /*!< Enable Prefetch Buffer */
;;;704        FLASH->ACR |= FLASH_ACR_PRFTBE;
000038  4a37              LDR      r2,|L1.280|
00003a  6812              LDR      r2,[r2,#0]
00003c  f0420210          ORR      r2,r2,#0x10
000040  4b35              LDR      r3,|L1.280|
000042  601a              STR      r2,[r3,#0]
;;;705    
;;;706        /*!< Flash 2 wait state */
;;;707        FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
000044  461a              MOV      r2,r3
000046  6812              LDR      r2,[r2,#0]
000048  f0220203          BIC      r2,r2,#3
00004c  601a              STR      r2,[r3,#0]
;;;708        FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
00004e  461a              MOV      r2,r3
000050  6812              LDR      r2,[r2,#0]
000052  f0420202          ORR      r2,r2,#2
000056  601a              STR      r2,[r3,#0]
;;;709     
;;;710        /*!< HCLK = SYSCLK */
;;;711        RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
000058  4a2e              LDR      r2,|L1.276|
00005a  6852              LDR      r2,[r2,#4]
00005c  4b2d              LDR      r3,|L1.276|
00005e  605a              STR      r2,[r3,#4]
;;;712          
;;;713        /*!< PCLK2 = HCLK */
;;;714        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
000060  461a              MOV      r2,r3
000062  6852              LDR      r2,[r2,#4]
000064  605a              STR      r2,[r3,#4]
;;;715        
;;;716        /*!< PCLK1 = HCLK */
;;;717        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
000066  461a              MOV      r2,r3
000068  6852              LDR      r2,[r2,#4]
00006a  f4426280          ORR      r2,r2,#0x400
00006e  605a              STR      r2,[r3,#4]
;;;718        
;;;719        /*!< PLLCLK = 8MHz * 9 = 72 MHz */
;;;720        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
000070  461a              MOV      r2,r3
000072  6852              LDR      r2,[r2,#4]
000074  f422127c          BIC      r2,r2,#0x3f0000
000078  605a              STR      r2,[r3,#4]
;;;721        RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL9);
00007a  461a              MOV      r2,r3
00007c  6852              LDR      r2,[r2,#4]
00007e  f44212e8          ORR      r2,r2,#0x1d0000
000082  605a              STR      r2,[r3,#4]
;;;722    
;;;723        /*!< Enable PLL */
;;;724        RCC->CR |= RCC_CR_PLLON;
000084  461a              MOV      r2,r3
000086  6812              LDR      r2,[r2,#0]
000088  f0427280          ORR      r2,r2,#0x1000000
00008c  601a              STR      r2,[r3,#0]
;;;725    
;;;726        /*!< Wait till PLL is ready */
;;;727        while((RCC->CR & RCC_CR_PLLRDY) == 0)
00008e  bf00              NOP      
                  |L1.144|
000090  4a20              LDR      r2,|L1.276|
000092  6812              LDR      r2,[r2,#0]
000094  f0127f00          TST      r2,#0x2000000
000098  d0fa              BEQ      |L1.144|
;;;728        {
;;;729        }
;;;730    
;;;731        /*!< Select PLL as system clock source */
;;;732        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00009a  4a1e              LDR      r2,|L1.276|
00009c  6852              LDR      r2,[r2,#4]
00009e  f0220203          BIC      r2,r2,#3
0000a2  4b1c              LDR      r3,|L1.276|
0000a4  605a              STR      r2,[r3,#4]
;;;733        RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
0000a6  461a              MOV      r2,r3
0000a8  6852              LDR      r2,[r2,#4]
0000aa  f0420202          ORR      r2,r2,#2
0000ae  605a              STR      r2,[r3,#4]
;;;734    
;;;735        /*!< Wait till PLL is used as system clock source */
;;;736        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
0000b0  bf00              NOP      
                  |L1.178|
0000b2  4a18              LDR      r2,|L1.276|
0000b4  6852              LDR      r2,[r2,#4]
0000b6  f002020c          AND      r2,r2,#0xc
0000ba  2a08              CMP      r2,#8
0000bc  d1f9              BNE      |L1.178|
0000be  e001              B        |L1.196|
                  |L1.192|
;;;737        {
;;;738        }
;;;739      }
;;;740      else
;;;741      { /*!< If HSE fails to start-up, the application will have wrong clock 
;;;742             configuration. User can add here some code to deal with this error */    
;;;743    
;;;744        /*!< Go to infinite loop */
;;;745        while (1)
0000c0  bf00              NOP      
                  |L1.194|
0000c2  e7fe              B        |L1.194|
                  |L1.196|
;;;746        {
;;;747        }
;;;748      }
;;;749    }
0000c4  4770              BX       lr
;;;750    #endif
                          ENDP

                  SetSysClock PROC
;;;190      */
;;;191    static void SetSysClock(void)
0000c6  b510              PUSH     {r4,lr}
;;;192    {
;;;193    #ifdef SYSCLK_FREQ_HSE
;;;194      SetSysClockToHSE();
;;;195    #elif defined SYSCLK_FREQ_20MHz
;;;196      SetSysClockTo20();
;;;197    #elif defined SYSCLK_FREQ_36MHz
;;;198      SetSysClockTo36();
;;;199    #elif defined SYSCLK_FREQ_48MHz
;;;200      SetSysClockTo48();
;;;201    #elif defined SYSCLK_FREQ_56MHz
;;;202      SetSysClockTo56();  
;;;203    #elif defined SYSCLK_FREQ_72MHz
;;;204      SetSysClockTo72();
0000c8  f7fffffe          BL       SetSysClockTo72
;;;205    #endif
;;;206     
;;;207     /*!< If none of the define above is enabled, the HSI is used as System clock
;;;208        source (default after reset) */ 
;;;209    }
0000cc  bd10              POP      {r4,pc}
;;;210    
                          ENDP

                  SystemInit PROC
;;;160      */
;;;161    void SystemInit (void)
0000ce  b510              PUSH     {r4,lr}
;;;162    {
;;;163      /*!< RCC system reset(for debug purpose) */
;;;164      /*!< Set HSION bit λֵ83H   ڲ8M*/			  
;;;165      RCC->CR |= (uint32_t)0x00000001;	  
0000d0  4810              LDR      r0,|L1.276|
0000d2  6800              LDR      r0,[r0,#0]
0000d4  f0400001          ORR      r0,r0,#1
0000d8  490e              LDR      r1,|L1.276|
0000da  6008              STR      r0,[r1,#0]
;;;166      /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
;;;167      RCC->CFGR &= (uint32_t)0xF8FF0000;  
0000dc  4608              MOV      r0,r1
0000de  6840              LDR      r0,[r0,#4]
0000e0  490e              LDR      r1,|L1.284|
0000e2  4008              ANDS     r0,r0,r1
0000e4  490b              LDR      r1,|L1.276|
0000e6  6048              STR      r0,[r1,#4]
;;;168      /*!< Reset HSEON, CSSON and PLLON bits */
;;;169      RCC->CR &= (uint32_t)0xFEF6FFFF;
0000e8  4608              MOV      r0,r1
0000ea  6800              LDR      r0,[r0,#0]
0000ec  490c              LDR      r1,|L1.288|
0000ee  4008              ANDS     r0,r0,r1
0000f0  4908              LDR      r1,|L1.276|
0000f2  6008              STR      r0,[r1,#0]
;;;170      /*!< Reset HSEBYP bit */
;;;171      RCC->CR &= (uint32_t)0xFFFBFFFF;
0000f4  4608              MOV      r0,r1
0000f6  6800              LDR      r0,[r0,#0]
0000f8  f4202080          BIC      r0,r0,#0x40000
0000fc  6008              STR      r0,[r1,#0]
;;;172      /*!< Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
;;;173      RCC->CFGR &= (uint32_t)0xFF80FFFF;
0000fe  4608              MOV      r0,r1
000100  6840              LDR      r0,[r0,#4]
000102  f42000fe          BIC      r0,r0,#0x7f0000
000106  6048              STR      r0,[r1,#4]
;;;174      /*!< Disable all interrupts */
;;;175      RCC->CIR = 0x00000000;
000108  2000              MOVS     r0,#0
00010a  6088              STR      r0,[r1,#8]
;;;176        
;;;177      /*!< Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
;;;178      /*!< Configure the Flash Latency cycles and enable prefetch buffer */
;;;179      SetSysClock();
00010c  f7fffffe          BL       SetSysClock
;;;180    
;;;181    }
000110  bd10              POP      {r4,pc}
;;;182    
                          ENDP

000112  0000              DCW      0x0000
                  |L1.276|
                          DCD      0x40021000
                  |L1.280|
                          DCD      0x40022000
                  |L1.284|
                          DCD      0xf8ff0000
                  |L1.288|
                          DCD      0xfef6ffff

                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                  SystemFrequency
                          DCD      0x044aa200
                  SystemFrequency_SysClk
                          DCD      0x044aa200
                  SystemFrequency_AHBClk
                          DCD      0x044aa200
                  SystemFrequency_APB1Clk
                          DCD      0x02255100
                  SystemFrequency_APB2Clk
                          DCD      0x044aa200
